Overview
Write parametric Verilog HDL code for the provided FIR
filter datapath (a) at the behavioral level and (b) at the structural level. The logic receives WL-bit signed input x every clock cycle and produces output y every clock cycle. The three filter coefficients 'a0,' 'a1,' and 'a2' are WLc-bit signed values. Define them as parameters with the default values of a0=-3, a1=3, and a2=-4. Develop a testbench to validate your design, confirming its functionality using the following input values: x={-1, 2, 3, 4, -3, 5, -6, 8}. Please submit both your Verilog designs and the associated testbench, along with simulation waveforms depicting the inputs and outputs.