Overview
Assessment Brief Component 001 | KD5064 | Analogue Electronics Assignment | 2025-2026 Programme: Electrical and Electronic Engineering BEng/MEng (Hons) Module Code: KD5064 Module Title: Analogue Electronics and Instrumentation Distributed on: 28-01-2026 Submission Time and Date: To be submitted by 23:59 GMT on [18-05-2026] Word Limit: Maximum 3000 words (Font size 11). Figures, circuit diagrams, tables, simulation screenshots, and appendices are not included in the word count. Weighting This Component 001 accounts for 50% of the total mark for this module Submission of Assessment Electronic Management of Assessment (EMA): Please note if your assignment is submitted electronically it will be submitted online via Turnitin by the given deadline. You will find a Turnitin link on the module’s eLP site. Academic Misconduct The Assessment Regulations for Taught Awards (ARTA) contain the Regulations and procedures applying to cheating, plagiarism and other forms of academic misconduct. The full policy is available at here. You should take particular attention to the Academic Misconduct Policy document in section 3.6, with regards to using Artificial Intelligence Systems in your assignments. You are reminded that plagiarism, collusion and other forms of academic misconduct as referred to in the Academic Misconduct procedure of the assessment regulations are taken very seriously. Assignments in which evidence of plagiarism or other forms of academic misconduct is found may receive a mark of zero. It is your responsibility to ensure that your assignment arrives before the submission deadline stated above. See the University policy on late submission of work. Learning Outcomes assessed in this assessment: Knowledge & Understanding 1. Demonstrate the application of knowledge in the design of instrumentation, and sensor systems with reference to real world problems (AHEP 4, C1). Intellectual / Professional skills & abilities 2. Mathematically model system-level and circuit solutions for instrumentation and analogue electronic systems (AHEP 4, C3). 3. Simulate, build and test circuitry using simulation and practical lab equipment (AHEP 4, C12, M12). 4. Analyse the specification and performance requirements necessary for sensors, instrumentation and general circuit operation within a regulatory framework (AHEP 4, C2,C13). Assessment Brief Assessment Overview: This coursework evaluates your ability to design, analyse, simulate, build, and critically assess key analogue electronic circuits. You are required to complete both Task 1 and Task 2. Your report must include: • Circuit theory and mathematical derivations • Component selection with justification • OrCAD simulations • Practical measurements (breadboard implementation) • Critical evaluation of discrepancies and limitations • Appropriate referencing (IEEE style) Task 1: Active Filter Design (50 Marks) You will design, simulate, and practically evaluate an active filter system. To introduce engineering design freedom, you must choose ONE of the following filter options: Choose ONE Filter System: Option A — Cascaded Sallen–Key High Pass Filter (HPF) + RC Low Pass Filter (LPF) (Wideband Band-Pass Filter (BPF) Design the HPF and LPF stages independently using the ratio method and combine them to achieve a wideband BPF (e.g. 20 Hz-20 kHz). Option B — Infinite Gain Multiple Feedback (IGMF) Band-Pass Filter Design the IGMF BPF for a chosen mid-band frequency (between 500 Hz and 5 kHz) and a defined bandwidth. Assessment Criteria: Task Achievement 1.1 Literature Review Provide a concise review discussing: • Principles of the chosen topology • Typical industrial applications Maximum Marks 8 Marks • Importance of Q-factor, damping ratio, bandwidth • Limitations of real op-amps (slew rate, gain-bandwidth (GBW), offsets) 1.2 Analytical Design • Derivation of key transfer functions • Cut-off/mid-band frequencies, Q-factor, damping ratio 10 Marks • Complete component selection with justification • Expected magnitude and phase responses 1.3 OrCAD Simulation • Bode magnitude & phase plots • Input/output time-domain waveforms at three test frequencies (including two cut-off frequencies) 12 Marks • Discussion of passband/stopband behaviour • Identification of GBW or slew-rate limitations (with reasoning) 1.4 Practical Implementation Build the circuit on the breadboard and record: • Measured Bode plot values (gain/phase shift angle vs frequency table) 12 Marks Component 001 | KD5064 | Analogue Electronics Assignment | 2025-2026 Assessment Brief Component 001 | KD5064 | Analogue Electronics Assignment | 2025-2026 • Captured time-domain waveforms at three test frequencies (same as the simulation) using an oscilloscope. • Commentary on measurement technique and uncertainty 1.5 Open-Ended Evaluation Critically evaluate your design. Discuss at least Three of the following: • Impact of component tolerance on measured Q/fc • Differences between simulation and practical behaviour • Sourcing/availability trade-offs for R/C values • Effects of op-amp limitations • How you would improve the design (e.g., Q tuning, cascaded stages) 8 Marks Subtotal 50 Marks Task 2: BJT Amplifier Design, Modelling, Simulation, and Practical Evaluation (50 Marks) You are required to design, analyse, simulate and practically evaluate two Common-Emitter amplifiers using two different biasing methods, chosen from the following three design approaches: Allowed Biasing Design Methods 1. Feedback Bias 2. Potentiometer Bias using the 10 Base Currents Method 3. Potentiometer Bias using the Norton Equivalent Method You must analyse, simulate, and build both amplifiers using the same design specification. Specification (Fixed for Both Amplifiers): Parameters/Conditions Value Supply Voltage VCC = 10 V Emitter voltage target VE ≈ 1–3 V (justify your choice) Base-Emitter Voltage VBE = 0.7 V Desired DC Collector Current ICQ = 0.3–0.8 mA (you select a value with justification) Input Signal 200–300 mV peak-to-peak sinusoid Operation Target Maximum Symmetrical Swing (MSS) Collector load resistor RL = 100 kΩ (fixed) Capacitors shown in your design must remain. Assessment Brief Component 001 | KD5064 | Analogue Electronics Assignment | 2025-2026 Assessment Criteria: Task Achievement Maximum Marks 2.1 Literature Review Summarise: • Principles of BJT operation • Comparison of the biasing techniques • Advantages/disadvantages regarding β stability and temperature robustness • Role of RE, emitter degeneration, and small-signal models 8 Marks 2.2 DC Design & Bias Point Analysis For both amplifiers: • Derive RC, total emitter resistance (REtot), and all bias resistors • Draw DC voltage diagrams with AC superimposed • Explain MSS and justify your chosen operating point 8 Marks 2.3 Small-Signal Modelling Include: • Hybrid-π model sketches • Calculation of re, input resistance and AV • Discussion of linearity and influence of RE1/RE2 (split emitter design allowed) 10 Marks 2.4 OrCAD Simulation For each amplifier: • Bias-point verification • AC gain simulation • Key node voltages and waveforms • Percentage error between designed ICQ and simulated ICQ • Explanation of differences 8 Marks 2.5. Practical Implementation You must: • Build both circuits • Measure the actual transistor β (recording method required) • Measure DC node voltages (VB, VE, VC) • Measure AC gain • Compare with simulation and theory, highlighting reasons for discrepancies • Include photos, oscilloscope traces, and tables. 10 Marks 2.6 Open-Ended Exploration Choose Two questions to discuss: • How does variation in β influence stability in each design? • How would temperature changes affect the bias point? • How could emitter degeneration improve linearity or reduce distortion? • How could the design be optimised for gain-bandwidth? 6 Marks Subtotal 50 Marks Assessment Brief ASSESSMENT REGULATIONS You are advised to read the guidance for students regarding assessment policies. They are available online here. Late submission of work Where coursework is submitted without approval, after the published hand-in deadline, the following penalties will apply. For coursework submitted up to 1 working day (24 hours) after the published hand-in deadline without approval, 10% of the total marks available for the assessment (i.e.100%) shall be deducted from the assessment mark. Coursework submitted more than 1 working day (24 hours) after the published hand-in deadline without approval will be regarded as not having been completed. A mark of zero will be awarded for the assessment and the module will be failed, irrespective of the overall module mark. These provisions apply to all assessments, including those assessed on a Pass/Fail basis. The full policy can be found here. Word limits and penalties If the assignment is within +10% of the stated word limit no penalty will apply. The word count is to be declared on the front page of your assignment and the assignment cover sheet. The word count does not include appendices, glossary, footnotes, tables Please note, in text citations [e.g. (Smith, 2011)] and direct secondary quotations [e.g. “dib-dab nonsense analysis” (Smith, 2011 p.123)] are INCLUDED in the word count. Students must retain an electronic copy of this assignment (including ALL appendices) and it must be made available within 24hours of them requesting it be submitted. The full Word Limit Policy is available here. Group Work The group work policy can be found here Component 001 | KD5064 | Analogue Electronics Assignment | 2025-2026